In digital systems for recording and playing back audio signals, with or without broadcast and reception steps, coding/decoding devices are useful and widely used to reduce memory or bandwidth requirements. Such devices generally extract from one or more digital input signals, a set of decoded signals (channels), by performing an appropriate decoding algorithm.
For example, the well known Dolby Pro Logic system permits the extraction of four to six decoded channels from two codified digital input signals. The decoding algorithm is based on a processing that derives from the particular coding system used and may be generically illustrated by way of a diagram as shown in FIG. 1. Based on two sequences or digital input streams, referred to as Left.sub.-- total and Right.sub.-- total, respectively, four fundamental output channels are extracted, indicated as Left, Right, Central and Surround, respectively.
A Dolby Pro Logic decoding system may be exemplified as shown in FIG. 2. The input signals Left.sub.-- total and Right.sub.-- total are, as mentioned, digital audio signals and thereby have a peculiar band of frequencies that vary from 0 to 20 KHz and a sampling frequency that may be of 32, 44.1 or 48 KHz, according to most common system embodiments.
The block CONTROL of FIG. 2 represents the processing circuitry to which the present invention relates. A typical processing circuit, represented by the block CONTROL in the scheme of FIG. 2, is shown by way of a functional diagram in FIG. 3, using a common Simulink symbology in a Matlab environment.
By observing the functional scheme of FIG. 3, the first processing on the two input signals is a bandpass filtering with a passband from 200 Hz to 5 KHz. After the filtering, from the two resulting signals, the sum (corresponding to the Central channel) and the difference (corresponding to the Surround channel) are calculated, and thereafter the absolute value of the four signals thus obtained is determined. The following stage is a lowpass filtering stage, typically with a time constant of 3 msec, equivalent to a cut-off frequency of about 50 Hz.
The value of the time constant and therefore of the cut-off frequency is preferably normalized to the Nyquist frequency which represents the effective signal band in sampled systems. The Nyquist frequency is equal to a half of the implemented sampling frequency. For the example considered, the sampling frequency is 5.125 KHz and therefore the Nyquist frequency is 5.125/2.congruent.2.7 KHz. Since a time constant of 3 msec corresponds to a cut-off frequency of 1/2.PI.3=53 Hz, the portion of the bands that are not attenuated by the lowpass filter is about 53/2700, that is approximately 2% of the whole signal spectrum.
At this stage of the processing, the high frequency components contained in the codified input signals have been attenuated and the resulting signals are varying slowly and have a trend that coincides approximately to the envelop of the input signals. Such sequences are thereafter undersampled, for example by a factor of 8, and a computing phase begins that has the purpose of determining the two output values, VLR and VCS, which indicate the ratio between the middle levels of the Left and Right, respectively, and those of the Central and Surround channels.
The computational algorithm of such parameters is as follows:
If LT&gt;RT then VLR=1-(RT/LT) PA1 If RT&gt;LT then VLR=(LT/RT)-1 PA1 If CT&gt;St then VCS=1-(ST/CT) PA1 If ST&gt;CT then VCS=(CT/ST)-1 PA1 If VLR&gt;0 THEN Left&gt;Right PA1 If VLR&lt;0 THEN Right&gt;Left PA1 If VCS&gt;0 THEN Central&gt;Surround PA1 If VCS&lt;0 THEN Surround&gt;Central PA1 a differentiator having first inputs through which a first sequence of digital input data (a(n)) is applied, second inputs and corresponding outputs of a sequence of digital values corresponding to the difference between two digital input values; PA1 a multiplier by a constant having inputs coupled to the outputs of the differentiator and corresponding outputs; PA1 an adder having first inputs coupled to the outputs of the multiplier by a constant, second inputs and corresponding outputs onto which is produced the (y(n)) digital ratio value; PA1 a first array of bistable, one clock cycle delay circuits having inputs coupled to the outputs of the adder and as many outputs coupled to second inputs of the same adder; PA1 a second array of bistable, one clock cycle delay circuits having inputs coupled to the outputs of the adder and as many outputs; PA1 a multiplier circuit having first inputs coupled to the outputs of the second array of bistable circuits and second inputs through which is fed the other sequence of input digital data (b(n)) and as many outputs coupled to second inputs of the differentiator.
The values of VLR and VCS vary between -1 and 1 and have the following meaning:
This algorithm, in itself simple, may not be so when considering a hardware implementation thereof. In fact, it entails the computation of a ratio, therefore the execution of a binary division which is a burdensome operation in terms of hardware requirements and of the clock pulses required for its execution.
In case of implementing the algorithm with a general purpose DSP (Digital Signal Processor), such as for example Motorola's 56000 family, the problem is resolved by resorting to the following equation: EQU log (a/b)=log a-log b
whereby the logarithm of the ratio between two numbers is equal to the difference of the respective logarithms. The result of the difference is converted back to the value of the argument a/b by way of the (exponential function: EQU exp (log (a/b))=a/b
Such a hardware implementation is feasible by the use of general purpose machines provided with installed logarithmic tables. This type of solution requires however many resources, chiefly in terms of the machine time required for computing the exponential function. When considering a hardware embodiment of such an algorithm, as is often the case in an audio playback/receiver, it becomes evident that this type of approach is rather expensive because of the memory requirement for storing the look-up table of the logarithmic function.